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this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.04 /feb. 99 hyundai semiconductor hy62uf16400/ hy62qf16400/ hy62ef16400/ hy62sf16400 series 256kx16bit full cmos sram preliminary description the hy62uf16400 / hy62qf16400 / hy62ef16400 / hy62sf16400 is a high speed, super low power and 4mbit full cmos sram organized as 262,144 words by 16bits. the hy62uf16400 / hy62qf16400 / hy62ef16400 / hy62sf16400 uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well-suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.5v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup(ll/sl-part) - 1.5v(min) data retention standard pin configuration - 48ball ubga product voltage speed operation standby current(ua) temperature no. (v) (ns) current(ma) ll sl ( c) hy62uf16400 3.0 70/85/100 15 20 4 0~70(normal) hy62uf16400-i 3.0 70/85/100 15 20 4 -40~85(e.t.) hy62qf16400 2.5 85/100/120 10 20 4 0~70(normal) hy62qf16400-i 2.5 85/100/120 10 20 4 -40~85(e.t.) hy62ef16400 2.0 100/120/150 10 20 4 0~70(normal) hy62ef16400-i 2.0 100/120/150 10 20 4 -40~85(e.t.) hy62sf16400 1.8 120/150/200 10 20 4 0~70(normal) hy62sf16400-i 1.8 120/150/200 10 20 4 -40~85(e.t.) note 1. e.t. : extended temperature, normal : normal temperature 2. current value is max. pin connection ( top view ) block diagram / lb io9 io10 / oe a0 a1 a2 nc / ub a3 a4 / cs io1 io11 a5 a6 io2 io3 vss io12 a17 a7 io4 vcc vcc io13 nc a16 io5 vss io15 io14 a14 a15 io6 io7 io16 nc a12 a13 / we io8 nc a8 a9 a10 a11 nc pin description pin name pin funtion pin name pin funtion /cs chip select i/o1~i/o16 data input/output /we write enable a0~a17 address input /oe output enable vcc power(3.0v/2.5v/2.0v/1.8v) /lb low byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o16) nc no connection row decoder memory array 1024 x128x16 sense amp write driver output buffer i/o1 i/o8 i/o9 i/o16 decoder add input buffer a0 a17 / cs / oe / lb / ub / we
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 2 ordering information part no. speed power temp. package hy62uf16400llm 70/85/100 ll-part ubga hy62uf16400slm 70/85/100 sl-part ubga hy62uf16400llm-i 70/85/100 ll-part e.t. ubga hy62uf16400slm-i 70/85/100 sl-part e.t. ubga hy62qf16400llm 85/100/120 ll-part ubga hy62qf16400slm 85/100/120 sl-part ubga hy62qf16400llm-i 85/100/120 ll-part e.t. ubga hy62qf16400slm-i 85/100/120 sl-part e.t. ubga hy62ef16400llm 100/120/150 ll-part ubga hy62ef16400slm 100/120/150 sl-part ubga hy62ef16400llm-i 100/120/150 ll-part e.t. ubga hy62ef16400slm-i 100/120/150 sl-part e.t. ubga hy62sf16400llm 120/150/200 ll-part ubga hy62sf16400slm 120/150/200 sl-part ubga hy62sf16400llm-i 120/150/200 ll-part e.t. ubga hy62sf16400slm-i 120/150/200 sl-part e.t. ubga note 1. e.t. : extended temperature, blank : normal temperature absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage -0.2 to 3.6 v vcc power supply -0.2 to 4.0 v t a operating temperature 0 to 70 c hy62uf16400 hy62qf16400 hy62ef16400 hy62sf16400 -40 to 85 c hy62uf16400-i hy62qf16400-i hy62ef16400-i hy62sf16400-i t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder lead soldering temperature & time 260 5 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability.
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 3 recommended dc operating condition symbol parameter product min. typ. max. unit vcc supply voltage hy62uf16400-(i) 2.7 3.0 3.3 v hy62qf16400-(i) 2.2 2.5 2.8 v hy62ef16400-(i) 1.8 2.0 2.2 v hy62sf16400-(i) 1.6 1.8 2.0 vss ground hy62uf16400-(i) 0 0 0 v hy62qf16400-(i) hy62ef16400-(i) hy62sf16400-(i) v ih input high voltage hy62uf16400-(i) 2.2 - vcc+0.2 v hy62qf16400-(i) 2.0 - vcc+0.2 v hy62ef16400-(i) 1.6 - vcc+0.2 v hy62sf16400-(i) 1.4 vcc+0.2 v v il input low voltage hy62uf16400-(i) -0.2 (1) - 0.4 v hy62qf16400-(i) hy62ef16400-(i) hy62sf16400-(i) note : 1. vil = -1.5v for pulse width less than 30ns truth table i/o pin i/o1~i/o8 i/o9~i/o16 h x x x x not selected hi-z hi-z i sb , i sb1 l h h x x output disabled hi-z hi-z icc l x x h h hi-z hi-z l h l l h read d out hi-z h l hi-z d out icc l l d out d out l l x l h write d in hi-z h l hi-z d in icc l l d in d in note: 1. h=v ih , l=v il , x=don't care 2. ub, lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o 1 -i/o 8. when ub is low, data is written or read to the upper byte, i/o 9 -i/o 16. /cs /we /oe /lb /ub mode supply current
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 4 dc electrical characteristics vcc = 3.0v 10%/2.5v 10%/2.0v 10%/1.8v 10%, t a = 0 c to 70 c (normal)/ -40 c to 85 c (e.t.) sym parameter test condition min. typ. max. unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il / ub = v ih or /lb = v ih -1 - 1 ua icc operating hy62uf16400-(i) /cs = v il , vcc = 3.0v - 8 15 ma power hy62qf16400-(i) v in = v ih or v il vcc = 2.5v/2v/ - 5 10 ma supply hy62ef16400-(i) i i/o = 0ma 1.8v current hy62sf16400-(i) i cc1 average hy62uf16400-(i) /cs = v il, min duty cycle = 100% - - 80 ma operating hy62qf16400-(i) i i/o = 0ma - - 60 ma current hy62ef16400-(i) - - 40 ma hy62sf16400-(i) - - 35 ma i sb ttl hy62uf16400-(i) /cs = v ih - - 0.5 ma standby hy62qf16400-(i) - - 0.3 ma current hy62ef16400-(i) - - 0.3 ma (ttl input) hy62sf16400-(i) - - 0.3 ma i sb1 standby current /cs > vcc - 0.2v sl - 0.2 4 ua (cmos input) ll - - 20 ua v ol output hy62uf16400-(i) vcc = 3.0v i ol = 2.1ma - - 0.4 v low hy62qf16400-(i) vcc = 2.5v i ol = 0.5ma voltage hy62ef16400-(i) vcc = 2.0v i ol = 0.33ma hy62sf16400-(i) vcc = 1.8v i ol = 0.26ma v oh output hy62uf16400-(i) vcc = 3.0v i oh = -1.0ma 2.2 - - v high hy62qf16400-(i) vcc = 2.5v i oh = -0.5ma 2.0 - - v voltage hy62ef16400-(i) vcc = 2.0v i oh = -0.44ma 1.6 - - v hy62sf16400-(i) vcc = 1.8v i oh = -0.44ma 1.4 - - v note : typical values are at vcc = 3.0v/2.5v/2.0v/1.8v, t a = 25 c
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 5 ac characteristics vcc = 3.0v 10%, t a = 0 c to 70 c (normal)/ -40 c to 85 c (e.t.), unless otherwise specified -70 -85 -10 min. max. min. max. min max. 1 trc read cycle time 70 - 85 - 100 - ns 2 taa address access time - 70 - 85 - 100 ns 3 tacs chip select access time - 70 - 85 - 100 ns 4 toe output enable to output valid - 40 - 45 - 50 ns 5 tba /lb, /ub access time - 40 - 45 - 50 ns 6 tclz chip select to output in low z 10 - 10 - 20 - ns 7 tolz output enable to output in low z 5 - 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 5 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 30 ns 10 tohz out disable to output in high z 0 30 0 30 0 30 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 30 0 30 ns 12 toh output hold from address change 10 - 10 - 15 - ns 13 twc write cycle time 70 - 85 - 100 - ns 14 tcw chip selection to end of write 60 - 70 - 80 - ns 15 taw address valid to end of write 60 - 70 - 80 - ns 16 tbw /lb, /ub valid to end of write 60 - 70 - 80 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 50 - 55 - 75 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 25 0 30 0 35 ns 21 tdw data to write time overlap 30 - 35 - 45 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 5 - 10 - ns symbol parameter # read cycle write cycle unit
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 6 vcc = 2.5v 10%, t a = 0 c to 70 c (normal)/ -40 c to 85 c (e.t.), unless otherwise specified -85 -10 -12 min. max. min. max. min max. 1 trc read cycle time 85 - 100 - 120 - ns 2 taa address access time - 85 - 100 - 120 ns 3 tacs chip select access time - 85 - 100 - 120 ns 4 toe output enable to output valid - 45 - 50 - 60 ns 5 tba /lb, /ub access time - 45 - 50 - 60 ns 6 tclz chip select to output in low z 10 - 20 - 20 - ns 7 tolz output enable to output in low z 5 - 5 - 10 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 30 0 40 ns 10 tohz out disable to output in high z 0 30 0 30 0 40 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 30 0 40 ns 12 toh output hold from address change 10 - 15 - 15 - ns 13 twc write cycle time 85 - 100 - 120 - ns 14 tcw chip selection to end of write 70 - 80 - 100 - ns 15 taw address valid to end of write 70 - 80 - 100 - ns 16 tbw /lb, /ub valid to end of write 70 - 80 - 100 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 55 - 75 - 85 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 30 0 35 0 40 ns 21 tdw data to write time overlap 35 - 45 - 50 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 10 - 10 - ns symbol parameter # read cycle write cycle unit
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 7 vcc = 2.0v 10%, t a = 0 c to 70 c (normal)/ -40 c to 85 c (e.t.), unless otherwise specified -10 -12 -15 min. max. min. max. min max. 1 trc read cycle time 100 - 120 - 150 - ns 2 taa address access time - 100 - 120 - 150 ns 3 tacs chip select access time - 100 - 120 - 150 ns 4 toe output enable to output valid - 50 - 60 - 75 ns 5 tba /lb, /ub access time - 50 - 60 - 75 ns 6 tclz chip select to output in low z 20 - 20 - 20 - ns 7 tolz output enable to output in low z 5 - 10 - 10 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 30 0 40 0 50 ns 10 tohz out disable to output in high z 0 30 0 40 0 50 ns 11 tbhz /lb, /ub disable to output in high z 0 30 0 40 0 50 ns 12 toh output hold from address change 15 - 15 - 15 - ns 13 twc write cycle time 100 - 120 - 150 - ns 14 tcw chip selection to end of write 80 - 100 - 120 - ns 15 taw address valid to end of write 80 - 100 - 120 - ns 16 tbw /lb, /ub valid to end of write 80 - 100 - 120 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 75 - 85 - 100 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 35 0 40 0 50 ns 21 tdw data to write time overlap 45 - 50 - 60 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 10 - 10 - 10 - ns symbol parameter # read cycle write cycle unit
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 8 vcc = 1.8v 10%, t a = 0 c to 70 c (normal)/ -40 c to 85 c (e.t.), unless otherwise specified -12 -15 -20 min. max. min. max. min max. 1 trc read cycle time 120 - 150 - 200 - ns 2 taa address access time - 120 - 150 - 200 ns 3 tacs chip select access time - 120 - 150 - 200 ns 4 toe output enable to output valid - 60 - 75 - 100 ns 5 tba /lb, /ub access time - 60 - 75 - 100 ns 6 tclz chip select to output in low z 20 - 20 - 30 - ns 7 tolz output enable to output in low z 10 - 10 - 15 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 15 - ns 9 tchz chip deselection to output in high z 0 40 0 50 0 60 ns 10 tohz out disable to output in high z 0 40 0 50 0 60 ns 11 tbhz /lb, /ub disable to output in high z 0 40 0 50 0 60 ns 12 toh output hold from address change 15 - 15 - 30 - ns 13 twc write cycle time 120 - 150 - 200 - ns 14 tcw chip selection to end of write 100 - 120 - 170 - ns 15 taw address valid to end of write 100 - 120 - 170 - ns 16 tbw /lb, /ub valid to end of write 100 - 120 - 170 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 85 - 100 - 135 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 60 0 70 0 80 ns 21 tdw data to write time overlap 50 - 60 - 80 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 10 - 15 - 15 - ns ac test conditions t a = 0 c to 70 c (normal) / -40 c to 85 c (e.t.), unless otherwise specified parameter value input pulse level hy62uf16400-(i) 0.4v to 2.2v hy62qf16400-(i) 0.4v to 2.2v hy62ef16400-(i) 0.4v to 1.8v hy62sf16400-(i) 0.4v to 1.6v input rise and fall time 5ns input and output hy62uf16400-(i) 1.5v timing reference hy62qf16400-(i) 1.1v level hy62ef16400-(i) 0.9v hy62sf16400-(i) 0.8v output load cl = 30pf + 1ttl load symbol parameter # read cycle write cycle unit
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 9 ac test loads d out 3150 ohm cl(1) 3070 ohm v tm (2) note 1. including jig and scope capacitance 2. v tm = 2.8v for vcc = 3.0v : hy62uf16400-(i) v tm = 2.3v for vcc = 2.5v : hy62qf16400-(i) v tm = 1.8v for vcc = 2.0v : hy62ef16400-(i) v tm = 1.6v for vcc = 1.8v : hy62sf16400-(i) capacitance (temp = 25 c, f= 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs, /we, /oe) v in = 0v 8 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested timing diagram read cycle 1(note 1) addr oe cs ub,lb data out data valid trc tacs tclz toe tolz(5) taa toh tbhz(5) high-z tba tblz(5) tohz(5) tchz(5)
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 10 read cycle 2(note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3(note 1,3,4) cs tacs data valid tclz(5) tchz(5) data out notes: 1. /we is high for the read cycle. 2. device is continuously selected. /cs = v il 3. address valid is prior to or coincident with /cs transition low 4. /oe = v il 5. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. write cycle 1 addr cs data out twc tdw tohz(3,9) we data valid tdh twp(1) tas data in tcw twr(2) tbw tas taw ub,lb
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 11 write cycle 2 (note 5) tdw twhz we data valid tdh twp tas data in twr tcw taw (6) (7) twhz addr cs data out twc notes: 1. a write occurs during the overlap(twp) of a low /cs and low /we . 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low(/oe=v il ) 6. q(data out) is the same phase with the write data of this write cycle. 7. q(data out) is the read data of the next address. 8. if /cs is low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 9. transition is measured +200mv from steady state. this parameter is sampled and not 100% tested.
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 12 data retention electric characteristic t a =0 c to 70 c (normal)/-40 c to 85 c (e.t.) symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v 1.5 - 3.3 v i ccdr data retention current vcc=2.0v, /cs > vcc - 0.2v, ll - - 20 ua vss < v in < vcc sl - - 4 ua tcdr chip deselect to data retention time see data retention timing diagram 0 - - ns tr operating recovery time trc (2) - - ns notes: 1. typical values are under the condition of t a = 25 c. 2. trc is read cycle time. data retention timing diagram cs vdr cs>vcc-0.2v tcdr tr vss vcc 2.7/2.2v 1.8/1.6v vih data retention mode note : 1. 2.7v : hy62uf16400 and hy62uf16400-i 2.2v : hy62qf16400 and hy62qf16400-i 1.8v : hy62ef16400 and hy62ef16400-i 1.6v : hy62sf16400 and hy62sf16400-i reliability spec . test mode test spec. esd hbm > 2000v mm > 250v latch - up < -100ma > 100ma
hy62uf16400/hy62qf16400/hy62ef16400/hy62sf16400 series rev.04 / feb. 99 13 package information 48ball micro ball grid array package(m) b a a1 corner index area 6 5 4 3 2 1 a a b c d c c1 e 3.0 x 5.0 min f flat area g c1/2 h b1/2 b1 bump view top view 6 e1 e2 c e seating plane 4 a r 3 d(diameter) side view symbol min. typ. max. a - 0.75 - b - 3.75 - b1 9.77 9.82 9.92 c - 5.25 - c1 11.35 11.4 11.5 d 0.3 0.35 0.4 e 0.85 0.9 0.95 e1 0.6 0.65 0.7 e2 0.2 0.25 0.3 r - - 0.08 note 1. dimensioning and tolerancing per asme y14. 5m-1994. 2. all dimensions are millimeters. 3. dimension ? d ? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. solder ball array may be depopulated by omission balls from a full matrix. no shifting of matrix pattern is allowed. 6. this is a controlling dimension.

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